The present invention generally relates to electronic input/output (I/O) systems and methods, and, more specifically, relates to an I/O holdoff mechanism for use in a system where I/O device inputs are fed through a latency introducing bus.
The trend in electronic systems is towards miniaturization, as shown by the success in the marketplace of laptop and notebook computers, and hand-held video games. As the size of electronic systems shrinks, the pin count on their components becomes a significant limiting factor in further decreasing the size of the end product. Many systems are conserving pins by taking certain functions that used to occur in parallel format, and implementing these functions instead in a serial format. Electronic systems that have components that communicate via a serial bus are well-known in the prior art. In this manner a parallel data transfer that used to take eight data bits and a control bit for handshaking (nine bits total) can be implemented in serial format, which requires only two pins, one for serial data and another for the control bit. One specific example of reducing pin count by serializing functions previously accomplished in parallel is found in the VL82C480 chipset by VLSI Technology, Inc. To minimize the number of pins required to support a traditional Industry Standard Architecture (ISA) bus, the VL82C480 put the direct memory access (DMA) Request (DRQ) and Interrupt Request (IRQ) inputs that service the ISA bus into a parallel to serial converter, and used the resulting serial stream to determine the state of the DRQ and IRQ inputs. This serial stream had a dedicated bit for each DRQ and IRQ input, making for a large serial packet. In essence, the serial stream provides a series of snapshot of the state of all the pins in the system.
This method of serialization of DRQs and IRQs introduces latency to these signals due to the time required to serialize the data, the time required to shift out this large serial packet, and the time required to convert this serial data back to parallel format. For the case of a DMA Request, excessive latency could result in the DRQ input being asserted after the service of the DMA is no longer required, resulting in overflowing or underflowing the DMA data transfer. For the case of an Interrupt Request, excessive latency could cause the IRQ input to be asserted when an interrupt is no longer present, resulting in the CPU serving the Interrupt Request needlessly. For these reasons the latency of the serial stream is critical and must be minimized.
Even when latency is minimized, when many IRQ/DRQ signals transition at once, there will be a considerable amount of latency at the receiver before these transitions all arrive. For programs which depend on seeing real-time signal values at the I/O controller and DMA controller, the latency can cause significant errors in the system.